Systems Engineer Resume Templates in Word Format Free Download

Sample Template Example of Beautiful Excellent Professional Curriculum Vitae / Resume / CV Format with Career Objective, Job Description, Skills & Work Experience for Freshers & Experienced in Word / Doc / Pdf Free Download

Gracy Andre

309 Stratford Drive, Winter Springs, FL 64001

Home: 407-366-9876  Email: gracy.andre@panmetron.com                                  Cell: 321-277-9876

 

SUMMARY OF QUALIFICATIONS

HARDWARE SYSTEMS DESIGN ENGINEER with over 20 years experience in:

·         Embedded Hardware Systems Design: Architecture, Functional Partitioning, Embedded Processors, Algorithm Implementation, Functional Analysis/Simulation, Detailed Design and Physical Implementation.

·         FPGA and ASIC Design: Embedded Processing/Control, Image Processing, Video Processing Pipelines and Interfaces, Multilevel and Array Bus Systems, DDR2 Multiport Memory Controllers.

·         System Development: Technology and Trade Studies, Algorithm Evaluation and Simulation, Requirements Definition/Assessment, Write Design Specifications, Hardware Descriptions, HW/SW partitioning.

·         Systems Test – Test Procedures, Validation, Regression Testing, Data Collection, Trouble Reports

·         Test Software/Scripts – For Testing Hardware in FPGAs, Boards, and System Datapath.

·         Military and Commercial Products: Ground & Avionics Platforms. Staring/Scanning FLIR, Communication Sync/DDC/DUC, Embedded Control, Fire Control, Network (FC/GbE) Electronics.

·         Technical Leadership – Led up to 9 Engineers in numerous concept-to-product projects. Subsystem, Boards, FPGA, ASIC. Strong on Good Design Practices and Signal Integrity. PWB Design Support.

·         Clearance: DOD Active Top Secret/SCI

 TECHNICAL EXPERTISE

HW Systems – Communications, FLIR, Fire Control, Network, COTs and Custom Subsystems.

Communication – Rx/Tx Multichan DataPath FPGAs, Digital Rack HW Requirements, Selection, Configuration

Signal Processing – Digital Receiver Synchronization FPGA, FFT for ASIC (Module Compiler)

Image Enhancement – Design Lead: Sensor Interfaces, Frame Buffers, NUC/BPR, LAP, IP, Video Output

Algorithm Implementation – Translate, scale, and quantize into HW level code. Matlab LAP design.

FPGA - Xilinx V5FX, V2P, V4, Design, Embedded Processor, Constraints, Floor planning, Place/Route, Static Timing, Coregen (including MIG23 DDR2), HW CoSim. Quicklogic and some Altera experience.

ASIC - Semicustom .13 and .18um, 1-3.4 Mgates, Chip Express, LSI logic, LightSpeed, VLSI

Embedded Processors – Curtiss-Wright SBC/PMC COTs, Spectrum Signal Proc, Xilinx PPC(EDK), ARM7.

FLIRs– Scanning HTI BKIT, Staring 640x480 (Cooled), Interfacing: Video/Control, AFocal, Sensor Calibration.

Video – Channel Link, RS170 Timing, GenLock, Formatting, Pipelines, Interpolation, Instrumentation (DAS).

Frame Buffers – Designs for HTI BKIT FLIR. Line Buffers for Video Processing Synchronization.

Image Processors – Spatial: Pipelined and SIMD, Temporal: PPC Packet Switching Arrays

Memory Interfacing – Xilinx Mig23 DDR2 with Custom Multiport Controller, EMC (SRAM/FLASH/Regs).

Signal Integrity – DDR2 Lead, Design Rules, GHz SigXP Simulation/Jitter Analysis, SERDES Trades.

Bus Systems– Xilinx PLB: IPIC-EMIF Bridge, IPIC-Multiport DDR2, ARM7: PCI-AHB bridge.

Network Electronics – FC/GbE, Protocols, Switches, SerDes, Retimers, Copper/Optical links, Link Integrity.

PROFESSIONAL EXPERIENCE

ANC R&D, Palm Bay, FL (Harris Location) – HW Systems & FPGA Design                    (2/2010-Present)

·      Hardware systems architecture - Developed requirements and traded COTS components for the digital portion of a communication system. Created digital component interconnect spreadsheet. Completed successful PDR package.

·         Communications FPGAs – Developed requirements, architecture, detailed design, and SW interface. Implemented multichannel, data-path packet switching Rx and Tx on Virtex 5 FPGAs including simulation, integration, and test.

·         Data-Path Testing - Completed multichannel data-path testing, verifying correct dataflow and integrity. Modified C and C++ code running on VxWorks to enhance tests.

·         System Test and Validation – Ran, reviewed, and edited Test Procedures. Performed data collection to support systems engineering validation efforts.

DRS OPTRONICS, RSTA, Orlando/Palm Bay, FL – Sr Principal Engineer                           (2006-2009)

·         Image Enhancement – Led 3 FPGA and 1 Elect Engineers. Successful Completion of Adv FLIR Image Enhancement System. Roles: HW Subsystem Architecture Lead, FPGA Lead and Detailed Design. Did Requirements/Architecture for PWB/FPGA including Image Processing, Embedded CPU, Sensor/Video Interfaces, Format Conversion/Interpolation. Led DDR2 Signal Integ, Supported 2 PWB Design Engineers.

·         Frame Buffer / Instrumentation FPGA – Successful Completion of Design, Integration and Fielding on a modified COTS Module. Requirements, Architecture and Design for FLIR Frame Buffer and Channel Link DAS Video. Wrote Design Description.  Worked vendor design kit issues. Coordinated with Systems and Software in regular meetings. Defined SW Interface. Designed Test Pattern End-to-end verify capability.

·         Algorithm Implementation into FPGA – Took a Complex Filter and designed HW Level Matlab code (AccelDSP) for buffering sequencing, processing and coordination with another algorithm stage. Verified Scaled Floating point. Quantized code and verified FPGA against System Level Simulation.

·         Algorithm Integration – Integrated Development FPGA code into Real Time Image Processing System. Bonus: Overall Performance Factor: 2009=1.25, 2008=1.03, 100% Objectives Accomplished.

HARRIS CORP, GCSD, Palm Bay FL– Electrical Engineer 4                                                          (2003-2006)

·         Communications FPGA – Large FPGA redesign for Digital Receiver Synchronization. Did up front study of requirements and existing code, Preliminary Design with a modified architecture to accommodate new requirements. Partitioned design effort, carried out detailed design, synthesis, place/route and verified functionality with simulation and laboratory testing to a successful conclusion

·         Gigabit Signal Integrity – Analysis and Allegro SigNoise simulations for electro-optical links. Extensive work on Jitter Analysis (including Deterministic and Random) and SerDes trade studies. Ran IBIS and HSPICE models for Xilinx Rocket I/O. Worked end-to-end compliance analysis for FC 1G/2G and GbE.

·         GbE Switches – Architecture level design using COTS devices and software. Including Layer 3 support. Did block diagram, parts list, power estimate and layout. Worked Ipv6 bridge issues for Ipv6 over FC/GbE.

·         FC Switch Server ASIC – Source Synchronous interface design, Functional Simulation with NCSIM. Wrote Perl script to verify frame content and automate batch runs, vector generation, and results tabulation. Formality FPGA-ASIC RTL-RTL and RTL-Gates verification, Code coverage with Verification Navigator.

SYNOPSYS INC, Orlando FL  - Staff IC Design Engineer                                                     (2000-2002)

·         Designed Bridge Module, PCI to AHB Bridge - Concept to RTL and Verification, Top level design partitioning/block diagram and then detailed design of AHB Master and Slave Modules.

·         Processor Design Lead for .18um Network ASIC - ~1 Million gate ASIC, FPGA prototype, Concept to Synthesized RTL, Designed Computer Architecture (ARM7 CPU w/AHB) Lead for  interface IP. Designed ARM control/interfaces,  internal proprietary bus bridge. Manchester Encoder/Decoder. First pass success.

·         Multiplier and Micro-controller PC Design – Viewlogic and VHDL Design, Verilog Test bench, DC Synthesis and ModelSim Simulation/Verification. Implemented with Theseus NCL logic.

·         Designed FFT  Radix 2, 4, and 8 Butterflies using Module Compiler - Synthesized arithmetic configurations for optimizing Area, Delay, Latency, and Power with Module Compiler.

·         Design Modifications for Repairable memory – 3.4 million gates, .13um Communications ASIC.

LOCKHEED MARTIN, Orlando FL  - Sr. Staff Design Engineer                                          (1981-2000)

·         Embedded Processor Design Lead (Arrowhead 2000) – Requirements, Architecture, Specifications

·         Advanced Image Processor (IR&T 1999) – Concept for pipelined spatial (FPGA) and Temporal (Altivec)

·         Image Processor Design Lead (IR&T 1997-98) – Designed Subsystem with Spatial and Temporal processor arrays based on GAPP-IV SIMD and PPC603 Arrays. Developed advanced array processing bus (2 patents). Designed Chip Express LPGA bus interface ASIC. Led 9 Engineers to successful completion.

·         Embedded DSP Design Lead (Sniper ATP  Program 1995-96) – PWB TMS320C40 / Quicklogic FPGAs

·         Designed I/O and Timing FPGAs (Advanced FLIR IR&T Program 1994-95) – Quicklogic.

·         Image Manager Module and ASIC Design (1992-94) - Dual C40 PWB and Image Window ASIC (LSI)

·         Embedded SPARC Design Lead Fusion Test Bed (1990-92) – General Purpose and Quad Vector Proc.

·         Embedded Processor Design, Various Programs including LANTIRN (1981-89)

·         VLSI Program (1984-1986) - Designed Z8002 Data Flow Controller ASIC in 3um Standard Cell

Education

Bachelor Science, Electrical Engineering Technology, Old Dominion University, Norfolk Va.

Emphasis on Digital Design and Microprocessors. Senior Project I8080 EEPROM download/burn station

Patents/Awards/Affiliations

Two Level Multi-tier System Bus (7,191,271), System Bus Transceiver Interface (7,336,700)

Two Meritorious (Top 120) Achievement awards (Martin Marietta), IEEE Member

TECHNICAL ADDENDUM

Design and Programming Language Experience

·         Algorithm – Matlab/Simulink, Xilinx Sysgen, AccelDSP Design and Simulation

·         Hardware – VHDL, Verilog, Module Compiler, Abel

·         Software – C (some C++),  Assembly Language, Power-PC, SPARC, TMS320C40, M1750, Z8002, Z80.

·         Scripts – Perl, csh, tcsh, TeraTerm

Tool Experience

·         FPGA Design - Xilinx 11yrs, ISE, EDK, Plan Ahead,Sysgen,AccelDSP), Synplicity, QuartusII, Quicklogic(4yrs)

·         FPGA Design – Synopsys Synphony.

·         ASIC Design – Synopsys (6yrs, Design and Module Compiler,LEDA,Formality), LSI, Trans-EDA(Code Cover)

·         Simulation  - ModelSim(8yrs), NCSIM(7yrs), VCS, Matlab/Simulink, C(AccelDSP), Matlab/Xilinx HW Co-Sim

·         Signal Integrity – Cadence Allegro and SpecctraQuest (SigXP)

·         Capture – Block/FSM:Visual Elite, Schematic:Viewlogic, LSI, Orcad, Apollo/Mentor, Textual:VIM

·         Software – Xilinx EDK/SDK, VxWorks, Visual Studio Express C++ (code editing)

Board Level Lead/Design Experience

·         Image Enhancement Architecture Lead – Designed Board Architecture and wrote HW System Architecture Specification including PWB and FPGA, Cut and Pasted schematics for reuse and handed them off to board designers. Led  signal Integrity for DDR2 SDRAM. Supported board design efforts including multiple reviews.

·         Image Processor Design Lead  – GAPPIV SIMD Spatial Arrays and PPC Temporal Arrays. IPT lead for effort including Subsystem, Boards, and ASICs.

·         Embedded Processors Boards  – PPC603, TI DSP(C40), SPARC2, Mil-STD-1750, Z8002, Z80, PALs (10yrs)

·         Design Integrity – Sync techniques, clock dist, grounding, termination, min/max timing, loading, stackup.

·         Signal Integrity - Impedance control, Transmission Line Simulation (Specctraquest SigXP, Allegro Extraction).

Training, Studies and Self Study

·         Digital Communications – Multirate Signal Processing for Communication Systems, Frederic J Harris.

·         Image Processing – Studied Woods/Gonzalez/Eddins Books, Digital Image Processing and Using Matlab

·         Wireless Communications–Video class CDMA. Spread Spectrum. Book Wireless Communications (Rappaport)

·         DSP Book Club Classes – Modulation/Coding (Coding Part), Digital Signal Processing – FFT, FIR, IIR

·         High Speed Digital Design – Studied two Howard Johnson books and referenced for signal integrity work.

·         Networking – 802.3, MPLS, IPv6, Auto-Negotiation 1000Base-X, Switch Protocols include Layer 2/3 Switch, RIP, OSPF, Auto-Negotiation 1000Base-X, BGP-4, QoS, CoS, 802.1Q, 802.1X. 802.1S, VLAN, SNMP.

·         Serial Backplanes – PCI Express, RapidIO (Serial and Parallel), StarFabric, Infiniband, ASI

·         CAE Training -Formal Training from Synopsys for Design Compiler, Advanced Chip Synthesis, Prime Time, Physical Compiler, Module Compiler, Formality, VERA, Chip Architect, Floorplan Compiler, and other tools.

·         Matlab and Adv Matlab – Two one day classes

·         Certifications - Digital Design 1992, Xilinx 2001, ARM 2001, NCL 2000.

Test Equipment

·         Agilent 16801 Logic Analyzer, E4404 Spectrum Analyzer, Tektronix Oscilloscopes

·         Xilinx ChipScope

Download Resume Format