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ABir Jain

3325 Dawn Street                                                                                    
Colorado, NA 60114                                                           
Mobile (325)705-3598
Email: abir_jain252@gmail.com

OBJECTIVE
·   Experienced engineer with extensive experience in IC, semiconductor, and MEMS manufacturing,  packaging & assembly process, materials & characterization, reliability & failure analysis, mathematic & statistical analysis, and supplier management seeks a senior engineer position.


PROFESSIONAL EXPERIENCE

Consultant with StatRel 03/2011-present
  • Consulted with various MEMS sensor and semiconductor packaging, process flow, integration, packaging materials, reliability and failure analysis
Lead MEMS Design & Packaging Engineer 05/2011 – 08/11
Adecco Engineering & Technical ( contracted with GE Sensing, Fremont, CA 94539 )
  • Technology development of MEMS product (automotive, medical device) packaging & test, materials selection, BOM, FMEA, failure analysis
  • wafer level bonding process (anodic, glass frit), die attach process development
                                                                                                                              
Packaging & Reliability / FA Manager 02/2010-03/2011
VistaPoint Technologies, Flextronics International, Milpitas 95035
Successfully Delivered and Qualified Camera Modules to Top Customers
  • Developed CMOS sensor camera module packaging technology, selection of materials, define packaging & assembly FOL/EOL process flow
  • Led global reliability teams, developed reliability test plan, module  stress analysis, failure mechanism, reliability data modeling and lifetime analysis  
  • Led VistaPoint global Failure Analysis teams to address various failure issues associated materials, process, reliability, design, and drove corrective actions
  • Interfaced with customers, substrate and sensor suppliers for reliability issues

Sr. Process Engineer 12/2007-02/2010
Microprobe Inc., San Jose, CA
Successfully Delivered and Qualified Wafer Test Probe Card to Top Customers
  • Developed Intel 1268/1269/1270 and other key customers wafer test micro-probe card, packaging, and assembly process, BOM, and product qualification
  • Developed critical dimension of devices, process spec and definition, MEMS probe transient and steady state thermal analysis & reliability, procurement of tools, metrology development, and Gage R&R
  • HVM Process SPC control, and continuous improvement, FMEA, indicators and mass data statistical analysis, product characterization and failure analysis with external labs

Sr. Packaging Engineer 10/2005-11/2007
Intel Corporation, Assembly Technology Development, TMG, Chandler, AZ
Successfully delivered and qualified materials of 1268 & 1269 platforms, pioneered new FC and BGA materials, roadmap, proposed and defined materials & process flow of POP, stacked package, SIP
  • Acted as a technical lead engineer of materials core competency (SJR chip level packaging and board level assembly) in ATTD 
  • P1268 materials ownership: platform 1268 & 1269 flip chip development, underfill, Die side capacitor paste, SLI BGA lead free paste materials, materials compatibility and interaction
  • P1270 flip chip and assembly BGA SMT pathfinding technology development
  • Led modules, FA, Q&R, design, characterization lab, materials suppliers, and worked with subcon: development of assembly materials, process, root causes and troubleshooting in flip chip, die attach, wire bonding, ball attach, and SMT board level assembly
  • Selected and qualified assembly materials/process: programs including 1265 (Stacked CSP package), Freeville (board level lead free paste full qualification) and wireless WiMAX (die attach, FC/WB, molding, SMT) RF SIP, MCM, POP programs, supplier management
  • Designed package and materials meeting reliability/thermal/mechanical requirements, modeling.

Materials Quality Engineer 1/2004 – 9/2005
Tamura Kaken Corp., USA, Stockton, CA
  • Developed SMT electronic materials lead & lead free solder paste and flux/thinner, underfills
  • Supervised and managed analysis of materials and quality control by Thermal ARL, FTIR, SEM, Testing lab maintenance and calibration
  • GMP manufacturing process capability/control chart and SPC analysis, R&R
  • Quality improvement (ISO QMS 9001 & EMS 14001 and for Japanese company audits) and internal audit; Customer and internal corrective action, root causes, FMEA.

Post-Doc Materials Scientist, 01/2003-12/2003
R&D, ChemTrace Corporation, 44050 Fremont Blvd, Fremont, CA
  • Developed process and technology for semiconductor equipment parts precision cleaning, wet and dry etching, commercial services
  • Developed advanced application of analytic tools for contaminated & cleaned parts, and chemical solutions for semiconductor industry, report preparation and presentation for customers
  • Managed special research projects, coordinated research and set direction between material division and chemical division

Research and teaching assistant (ceramic composites), 01/1999-12/2002
Chemical Engineering, University of Missouri, Columbia
  • 3D mathematic simulation and modeling of mass and heat transfer in porous media: MLC materials body during binder burnout; Numerical computation of nonlinear, unsteady partial differential equations.
  • Pioneered novel approach: reaction and sintering process kinetics of high temperature ceramic composite materials coupled TGA, dilatometery and mass spectrometer
  • Improved dielectric property of semiconductor material SrTiO3, SrTiO3 synthesis, sintering, and coating, studied gas species, oxygen partial pressure effect on structure and properties
  • Evaluated effect of sintering gas and temperature profiles on electronic material (PZT) microstructure, properties, and density; silicon nitride and silicon carbide Si3N4/SiC material processing, coating, tape and slip casting, and sintering.

Research scholar, 07/1997-12/1998
Institute of Materials & Research Engineering, National University of Singapore (NUS)
  • KNbO3 single crystal growth at high temperature in melt solution by Czochralski (CZ) method.
  • Preparation, thermal analysis, crystallography and ferroelectrical behaviors of transparent LiNbO3 glass ceramics in SiO2 and TeO2 systems by DTA/TGA, DSC, XRD, AFM, FTIR

OTHER SKILLS
  • FORTRAN, C, MATLAB, FLOTHERM; Statistics: JMP, SAS, Design of experiments (DOE), MCA, Numerical Modeling, Solidwork

  • Analytical Tools: Thermo ARL analysis, LC-MS, GC, Mass Spectrometry, SEM/EDX, AFM, XRD, DTA, TGA, DSC, ICP-MS, Dilatometer, Brookfield Rheometer, BET, FTIR, Raman, UV, TOF-SIMS, CSAM, Curve Tracer, TDR

EDUCATION
·       Ph.D Chemical Engineering, University of Missouri, MO
  • B.S and M.S. Chemical Engineering, Dalian University of Technology



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