CPU Design Verification Engineer Sample Resume Format in Word Free Download

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Brenell Jones Email: brenell.jones@hotmail.com                                                                                                    Cell: (302)-810-7021            b_jones41@yahoo.com                                                                                                                   (302)-510-3024

                                                              

Ø  Objective

Seeking a fulltime position as a Design or Verification engineer in a learning and competitive environment to achieve excellence, to be resourceful and optimistic and to pursue a challenging career in front end VLSI design where my skills and experience will greatly enhance the company's success and my personal growth.

Ø  Summary

·   CPU Verification Engineer at Qualcomm Inc., Raleigh.

·   M.S in Electrical Engineering from San Jose State University, CA with VLSI coursework.

·   Knowledge of Computer Architecture, assembly language(MIPS, ARM) programming, RTL, familiar with System Verilog, VHDL, C/C++, Perl, TCL, familiar with 8085/8086

·   Good understanding of ASIC, Digital Design and CMOS processes.

Ø  Experience

·   Qualcomm Inc : CPU Design Verification Engineer, Raleigh                                      (April 2011 - Present)

ü Unit Level Functional Coverage

n Functional coverage of FMSTAT and VMOV instructions that focused on the FIFO and its interaction with the pipes

   using System Verilog.

n Coverage for Execution Unit covering the Write Back Stage using System Verilog.

n Coverage for Delay Stage of the WriteBack Stage using System Verilog.

n Coverage for the STATB interface that supplies data for store Instructions to the storage unit using System Verilog.

ü Unit Level Assertion

§   Assertions for the FIFOs implemented for FMSTAT and VMOV instructions in System Verilog.

ü Directed Testcases

§Memory Management Tests

   Debugging of Memory  Management tests implemented to verify proper behavior for various memory accesses for all

   instruction cache policy configurations. The test covered cache/MMU enabling & configuration and page table usage.   

   Worked in Perl and ARMv7 assembly language.

§Data Cache Maintainence Tests

  Debugging of Cache Maintenance tests implemented to verify the cache coherency on an ARMv7 processor which   

  consisted of 3 levels of caches- L0, L1 and L2. Tested coherency by analyzing data and tag updates corresponding to   

  each data cache command given to the system as the instruction under test along with its effect on the memory locations

  Worked in Perl and ARMv7 assembly language.

§ Memory Barrier Tests

   Debugging of Memory Barrier tests in Multiprocessor environment that focused particularly on the effects of DMB   

   and DSB commands on the snooped processor and on the non-issuing  processors. Worked in  Perl and ARMv7

   assembly language.

  

·   Fastrack Design : Hardware Engineering , San Jose                                                  (February 2011 - April 2011)

          Performing block level static timing analyses and learning floor planning using Magma Talus.

·   Database Management (Academic Technology, San Jose State University)           (Sep 2010 - February 2011)

           Worked on the design of a new database record using Adobe Filemaker PRO software.

Ø  Master’s Projects

·   Design of Dual Power Heterogeneous Processor                                                                  (Dec 2009-May 2010)

    Design a system which switches between two processors, one designed for high  performance  operations and  other for low 

    power operations. 

    Tools: Verilog Simulator(ModelSim) 

·   Design of 6-bit CMOS DAC in 45nm                                                                                      (Jan 2009-May 2009)

    Design, Simulation and Layout of 6 bit DAC using Thermometer Code in 45nm technology in a group of three.

    Created the Logic Design, Layout of 2-bit Thermometer Code, Switch, Amplifier and complete circuit. 

    Tools: Cadence IC Design. 

Brenell Jones Email: brenell.jones@hotmail.com                                                                                                    Cell: (302)-810-7021            b_jones41@yahoo.com                                                                                                                   (302)-510-3024

·   High Speed CMOS 27 bit Adder in 24um                                                                             (Aug 2008 – Dec 2008)

    Design and layout of a 27 bit adder at 4GHz clock frequency and implementing in 4 phase in a group of

    four. Created the Logic Design, Schematic & Layout of 3-bit  Adder and Propagation block. 

    Tools: Cadence IC Design.

                    

·   Design of Tomasulo's Processor                                                                                                   (Aug 2008 – Dec 2008)     

 The project involves Development, Simulation,Debugging, and Verification of a basic MIPS16S processor based on Tomasulo 

 algorithm. 

 Tools: Verilog Simulator. 

·   Design of 4x4 Keypad Scanner and Encoder                                                                      (Jan 2008 – May 2008)

 Designed and Implemented a 4-by-4 Keypad Scanner and Encoder to interface a matrix-type 4-row by 4-column eys) keypad

 to an 8-bit input port of a microprocessor system, individually. Tools: Verilog Simulator   

·   Design and Implementation of a 32 point FFT ASIC BLOCK Tools: Verilog Simulator            (Aug 2007 – Dec 2007)

Ø  Technical Skills

·   Languages & Tools     : Verilog , System Verilog, VHDL, C/C++, ModelSim, Cadense IC Design tool,  Magma Talus.

·   Scripting Language    : Perl, TCL.

·   Assembly Language  : ARM, MIPS, Intel 8085/8086

• Simulators                    : Verdi, ModelSim VHDL/Verilog simulator, NC Verilog.
• Synthesis                     : Synopsys Design Compiler.

Ø  Education

·  San Jose State University , San Jose, CA,USA                                                                                    (Aug 2007 – May 2010)

    M.S Electrical Engineering

    GPA : 3.52/4.0

        Coursework:

i.              Digital System Design and Synthesis.              ii.Computer Architecture.

    iii. ASIC CMOS Design                                          iv.High Speed CMOS circuits.

    v. Introduction to large Scale CMOS Design.        vi.Semiconductor Device and Physics.

·  Bhilai Institute of Technology, India

    Bachelor of Engineering Electronics and Telecommunication                                                                 (Aug 2002 – Dec 2006)

    GPA : 3.5/4.0

Ø  Activities/Accomplishments

·    Member of the ATI committee at San Jose State University

·    National Level Technical Paper Presentation on “Multi-Chip module Technology” at Nirma Institute of

    Technology, Ahmedabad, India and MPCCET, India.

·    Member of Technical and Cultural Committee in Bhilai Institute of Technology, India.

·    Hosted various functions as an Anchor organized in Bhilai Institute of Technology, India.

·    Served as House Captain in Delhi Public School, India.

·    Got Scholar Blazer for good academic performance in High School.

·    Received many certificates in Drawing and Painting.

(Reference upon request)

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