Sample Template Example of Beautiful Excellent Professional Curriculum Vitae / Resume / CV Format with Career Objective, Job Description, Skills & Work Experience for Freshers & Experienced in Word / Doc / Pdf Free Download
Download Resume Format
Payton
Email: payton.parul@yahoo.com
Contact No: 858-380-9876
Objective:
To contribute my technical skills and
commitment towards achieving
organization’s goals in the fields of ASIC/SOC
design verification.
Summary:
- Expertise
in Specman-e ,Verilog and good in SystemVerilog,
C, C++
- Strong
working knowledge of eVC development
- In
depth understanding of ARM based SOC
design and verification flow
- Working
knowledge on Mobile application processor verification
- Worked
on DDR controller, DMA and other memory systems in SOC
- Worked
on coverage analysis, testcase development, testcase failure
debugging
- Exposure
to formal verification, GLS, PA-GLS
- Fast
learner, strong debugging skills, team player and excellent communication
skills
Education:
Ø PG Certified course in Frontend
Logic Design by Cadence Design System in collaboration
with the University of California at
Santa Cruz and TIIT, March 2008.
Ø Bachelor of Engineering
(Electronics and Communications), SCET, Surat, 2002. Secured 74%.
Ø HSC(XII)
Gujarat State Board secured 86%.
Ø SSC(X)
Gujarat State Board secured 88%.
Technical
Skills:
o
EDA Tools: Specman, Cadence Nc-Sim, Cadence IFV, Cadence RTL- Compiler,
Cadence CTE, Synopsys VCS, ModelSim, Questasim, Verdi
- HDL,
HVL: Verilog
, Specman-e , SystemVerilog
- Programming
& Assembly: C, C++, 8085,
8086 & 8051
- Operating
Systems: Windows
9x/2000/XP/Vista, Linux, Unix
- Scripts: shell, perl
- Protocols: AMBA APB, AHB, AXI, ST Bus, DDR
Professional
Experience:
·
Design/Verification
Engineer : 1 Year
July 2010 to August 2011 , Sasken Communication Technology Ltd.,Bangalore
·
ASIC
Verification Engineer : 1 Year
·
June 08 to July 09, eInfochips Ltd, Bangalore
·
ASIC
Front end Trainee Engineer : 8 Months
Jul-07 to Mar 08 Time2Market Pvt. Ltd., Bangalore
Training is from Cadence Design Systems
(I) Pvt. Ltd. Which is certified by University of California Extension
Projects:
- SOC Verification : Consultant at ST-Ericsson from
Sasken: March 2011 to August 2011
Description:
Verification of dual core ARM cortex A9
based Multimedia Application Processor SOC which offers high application performance for
next generation smart phones.
Verification goal was to mainly test block
level integration that is register testing, interface level testing and system level checks related to
clock, reset, power management.
Contribution: Testplan,
testcase development, failure debugging of
all memories and memory subsystems
like DDR memory controller, Central DMA, FSMC (Flexible Static Memory
Controller), SDMMCI, Boot ROM , eSRAM, Backup RAM.
Tools: ARM
toolset, Cadence NC-Sim, Questasim,
Verdi
----------------------------------------------------
·
IP Verification : Consultant at Texas
Instruments from Sasken : Oct 2010 to Feb 2011
Description:
ADPLLLJM IP is Low Jitter
Phase Locked Loop. It has Programmable input dividers, post divider, fractional
loop multiplier and digitally controlled loop multiplier. Support clock gating
and power management modes. Digital lock indicator and relock from standby. It
also supports different clock outputs.
Contribution:
RTL simulation, testcase debugging
and environment update if needed.
GLS,PAGLS,PARTL
done for the same IP.
Tools: Cadence
NC-Sim, Modelsim
----------------------------------------------------
·
SOC Formal Verification : Consultant at Texas Instruments from Sasken:
Aug 2010 to Sep 2010
Description: Complex SoC containing different IPs . To check top level
connectivity and integration of different IPs Formal Verification
technique is used. Generation of assertions and constraints to detect
integration errors are automated.
Contribution:
Assertions failure debugging and fixing bugs
Tools: Cadence IFV
----------------------------------------------------
·
‘e’ Tool Validation : eInfochips Ltd:
July 2008 to June 2009
Description: Main project responsibility is to
develop eVC to validate client tool with respect to “e” Language support. All
the core priority syntax/construct identified by the client are verified for
it’s correct functionality in Tool.
Contribution:
Developing test bench architecture and identifying test scenarios.
Writing test-cases and developing testbench.
Responsible
for stimulus generation and checker mechanism for particular
syntax/construct few of them are pack-unpack, predefined methods, lists
methods etc.
Communicating and synchronizing with remote team.
Tools: Specman, NC-Sim, VCS
---------------------------------------------------
·
Asynchronous FIFO Design Verification :
eInfochips Ltd: June 2008-July 2008
Description: Supports FULL, EMPTY, ALMOST_FULL and
ALMOST_EMPTY status flags. Invalid read or write requests are rejected without
affecting the FIFO state. Optional count vector(s) provide visibility into
number of data words currently in the FIFO, synchronized to either clock
domain.
Contribution: Testbench
and testcases development based on eRM Methodology
Tools: NC-sim, Specman
----------------------------------------------------
·
DDR2 SDRAM Memory Controller :
Time2Market Pvt Ltd: Nov 2007 - Fab 2008
Description: Investigate
the different problems associated with the design and implementation of a DDR2 SDRAM
Memory Controller. In order to interface DDR2 SDRAM to the user,
controller is designed. It supports data transfers on both edges of each clock
cycle, effectively doubling the data through out of the memory device. It
operates at clock rate of 133 MHz and 64-bit data changing at both clock edges.
Contribution: RTL
coding of data path module in DDR controller
Tools: Cadence NC Sim , RTL Complier
Personal
Information:
Date of Birth: 21 / 06 / 1982
Sex: Male
Marital Status: Married
Email: payton.parul@yahoo.com
Contact No: 858-380-9876
Address: 309 Capricorn
Way, 17
San Diego, CA 92001
References:
Available on request.
Download Resume Format
0 comments:
Post a Comment