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JOY
SIEWIERA
01/20/2012
EMAIL: joy@hotmail.com
BACKGROUND SUMMARY
Digital Hardware Design Engineer with expertise in IC and logic design. Technical lead in DFT, experienced in logic synthesis, timing closure, coupled with strengths in RTL design/verification. Possesses strong debugging and problem solving skills. Very team oriented, hard working and quick self-learning professional
PROFESSIONAL EXPERIENCE
STANDARD MICROSYSTEMS (SMSC), Hauppauge, NY
2006-2012
IC Design Engineer/Senior Design Engineer, Computer Connectivity Products Div.
2009-2012
Technical Lead IC/RTL designer with concentration on DFT architecture and implementation on super speed USB2/USB3 hub and graphics chip with USB3, HDMI and RGB interfaces
Architected and implemented internal scan compression using Mentor methodology to reduce testing costs.
Architected and implemented at-speed scan testing to significantly reduce the number of functional tests needed otherwise. The test covered 21 clock domains on USB hub and 12 on graphics chip including clock crossing on synchronized clocks to max at-speed test coverage combined test coverage close to 99%.
Developed the full set of scan tests using Mentor ATPG testkompress tool, performed patterns verification on fully annotated design to make sure there is no timing related issues, supported ATE test program development. Tests successfully used in production.
Performed scan test compression logic generation (EDT logic) and integrated into RTL.
Successfully performed chip level scan insertion using Synopsys DFT compiler (DFTC).
Ran block level synthesis (DC)
Successfully worked on initial PT scripts on graphics chip (STA).
Performed gate-level ECOs, and formal verification using Formality
Functioned as IC/RTL designer USB2/USB3 to Gige Ethernet bridge
Specified and implemented chip test modes, internal scan with at-speed coverage and compression, boundary scan and JTAG, Memory BIST, test modes controlled via user-defined JTAG registers.
Inserted Memory BIST and JTAG/BSD logic using Mentor tool set and flow.
Performed verification of inserted logic boundary scan and MEM BIST tests, run functional regression tests to assure design integrity
Functioned as DFT company-wide consultant
Provided company-wide DFT expertise in concentration on internal scan architecture including at-speed testing, scan compression, patterns verifications and debugging, silicon failure diagnostics.
Developed at-speed scan architecture and methodology widely adopted across the company, proven in multiple silicon implementations. The methodology was documented and presented on companys technical conclave.
Established company specific DFT guidelines for internal scan
Developed RTL for configurable on-chip clock controller (OCC) used to control the clocks in at-speed scan testing including clock crossing (feature not supported in design provided by Synopsys)
IC Design Engineer/Project Engineer, Network Products Division
2006-2009
IC designer on family of USB and Ethernet standard products for regular and automotive applications: USB hubs, Ethernet hubs and switches, USB to Ethernet bridges, display controller with ARM7 core.
Responsible for full chip timing closure (STA) on multiple designs, which included timing constraints (SDC) and various case analysis specifications, supported clock tree synthesis in layout and timing ECOs. Developed PT TCL scripts set, including PT DMSA, which were reused on multiple designs.
Drove chip level DFT insertion, DRC debugging, faults analysis and patterns generation using Synopsys TMAX tool, run patterns verification using DPV methodology. Developed the simulations scripts to automate the patterns verification process - used on multiple designs.
AGERE SYSTEMS (Formerly Lucent Technologies), Allentown, PA
2000-2005
IC Design Engineer/Member of the Technical Staff Enterprise & Networking Div.
2004-2005
Lead IC designer on the USB2.0 Modem Device Controller, which included ARM7 core, DMA controller, USB2.0 device controller, on-chip USB PHY and Codec Digital Link Logic - first silicon was 100% functional.
Completed package and buffers selection, floor planning, pinout, IO ring design and verification, chip size and power estimate to meet USB2 spec tight power requirements.
Supervised custom cells development by specifying requirements, reviewing designs of custom blocks for internal voltage regulators, digital PLL (DPLL) etc.
Supported of USB2 PHY and DPLL integration for offshore RTL design team.
Consulted for offshore verification team to resolve USB2 PHY simulation issues.
Drove the Design for Testing (DFT) methodology by defining test modes, scan test development and integration at the full chip level, developing and debugging all ATE test vectors, to secure optimal ATE testing and maximum test coverage (> 97% for scan).
Performed netlist audits and formal verification with Formality to ensure design integrity.
Developed design constraints for ASTRO Timing Driven Layout (TDL), clock tree synthesis (CTS) to satisfy chip timing requirements
Completed full chip timing closure with Synopsys Primetime to make sure chip is clean from timing violations.
Performed clock jitter SPICE simulations to help identify the source of clock jitter.
RTL and IC Design Engineer, Computer Connectivity Division
2000-2004
Functioned as both RTL designer and IC designer on Modem Codec project for the digital block of the chip, RTL designer for bilingual 1394a/1394b Host/Link design and PHY development, IC designer for USB2.0 discrete PHY for two different technologies.
Performed RTL development/verification and IC design of entire SIO interface and trim control block. RTL designed in Verilog and audited with Verilint.
Designed innovative trimming scheme to aid calibration of critical analog parameters at package parts testing, which significantly reduced production testing time.
Worked closely with analog designers to assure that all design requirements are met.
Built Specman/ncsim/Verdi verification environment, Verilog behavioral model for the fuse block and developed exhaustive verification test suite using Specman e language to create test cases, to ensure design full verification.
Performed design synthesis, netlist audit (Spyglass), clock spine design, timing closure (also used Clockworks) and post layout netlist simulations. Final result - first silicon released to production with no respins.
Acquired knowledge of the 1394a/1394b Fire Wire Standard.
Worked on bilingual 1394a/1394b PHY design partitioning, completed RTL design/verification of 8B10B encoder/scrambler block.
Contributed in RTL design of Fire Wire (bilingual 1394a/1394b) Host/Link design for Apple IP and company standard products responsible for PHY/Link interface design. Contributions included RTL design, netlist audits, and verification. IP used successfully in various products.
Developed design constrains and completed design synthesis for USB2 PHY for two different technologies and performed design formal verification for RTL vs. pre layout and post layout netlist to ensure design integrity.
Utilized knowledge of the USB1.1, USB2.0 serial bus and UTMI I/O protocol specifications to be able to debug ATE testing issues.
Generated and debugged ATE tests for the family of Agere Fire Wire (FW) Standard Products FW80x/FW32x/FW420, including development of tests for speed signaling (common mode signaling tests for differential TPA/TPB for S200 and S400), exploit special 4X ATE test mode for S400 at-speed test to maximize tests coverage and minimize testing costs.
TECHNICAL/PROGRAMMING SKILLS
Verilog and VHDL hardware description languages.
Synopsys PT, PT SI, PT VX, DC, DFTC, TMAX, Formality.
Atrenta SpyGlass for RTL/netlist audit.
Cadence Verilog XL, NC Verilog Simulators
ADVICE (SPICE) circuit simulation tools.
C, Perl, TCL, Pascal, Specman e and assembly languages.
Sprint Verdi debugging tools, waveform viewers: signalscan, MTI, SimVision
Mentor Graphics tessent tool set, testkompress scan compression ATPG tool
EDUCATION AND PROFESSIONAL DEVELOPMENT
Master of Science in Electrical Engineering
City University of New York (CUNY), New York City, NY GPA: 3.7/4.00.
Masters Project: Implementation of the signal processing algorithm - DLX-based image processor system - hardware/software (VHDL/C) co design. Completed graduate level studies of the logic design/analysis, VHDL ALU design, Microprocessors, DSP, Image Processing and Recognition, Cryptology.
Postgraduate Program in Software Engineering
Rzeszow Institute of Technology, Rzeszow, Poland two-semesters program
Master of Science in Electronic Engineering
Academy of Mining and Metallurgy, Krakow, Poland
Company sponsored courses:
Verisity: Specman Basic Training, Advanced Specman Training
Synopsys: Chip Synthesis, Advanced Chip Synthesis, Design For Test (DFT), Basic Verilog with VCS, Advanced Verilog, Verilog Coding Styles for RTL, Chip-level Static Timing Analysis
Novas Debussy Debugging, Sprint Verdi latest features
Mentor Graphics Design for Testing, Silicon Test System
UNIX System Fundamentals
01/20/2012
EMAIL: joy@hotmail.com
BACKGROUND SUMMARY
Digital Hardware Design Engineer with expertise in IC and logic design. Technical lead in DFT, experienced in logic synthesis, timing closure, coupled with strengths in RTL design/verification. Possesses strong debugging and problem solving skills. Very team oriented, hard working and quick self-learning professional
PROFESSIONAL EXPERIENCE
STANDARD MICROSYSTEMS (SMSC), Hauppauge, NY
2006-2012
IC Design Engineer/Senior Design Engineer, Computer Connectivity Products Div.
2009-2012
Technical Lead IC/RTL designer with concentration on DFT architecture and implementation on super speed USB2/USB3 hub and graphics chip with USB3, HDMI and RGB interfaces
Architected and implemented internal scan compression using Mentor methodology to reduce testing costs.
Architected and implemented at-speed scan testing to significantly reduce the number of functional tests needed otherwise. The test covered 21 clock domains on USB hub and 12 on graphics chip including clock crossing on synchronized clocks to max at-speed test coverage combined test coverage close to 99%.
Developed the full set of scan tests using Mentor ATPG testkompress tool, performed patterns verification on fully annotated design to make sure there is no timing related issues, supported ATE test program development. Tests successfully used in production.
Performed scan test compression logic generation (EDT logic) and integrated into RTL.
Successfully performed chip level scan insertion using Synopsys DFT compiler (DFTC).
Ran block level synthesis (DC)
Successfully worked on initial PT scripts on graphics chip (STA).
Performed gate-level ECOs, and formal verification using Formality
Functioned as IC/RTL designer USB2/USB3 to Gige Ethernet bridge
Specified and implemented chip test modes, internal scan with at-speed coverage and compression, boundary scan and JTAG, Memory BIST, test modes controlled via user-defined JTAG registers.
Inserted Memory BIST and JTAG/BSD logic using Mentor tool set and flow.
Performed verification of inserted logic boundary scan and MEM BIST tests, run functional regression tests to assure design integrity
Functioned as DFT company-wide consultant
Provided company-wide DFT expertise in concentration on internal scan architecture including at-speed testing, scan compression, patterns verifications and debugging, silicon failure diagnostics.
Developed at-speed scan architecture and methodology widely adopted across the company, proven in multiple silicon implementations. The methodology was documented and presented on companys technical conclave.
Established company specific DFT guidelines for internal scan
Developed RTL for configurable on-chip clock controller (OCC) used to control the clocks in at-speed scan testing including clock crossing (feature not supported in design provided by Synopsys)
IC Design Engineer/Project Engineer, Network Products Division
2006-2009
IC designer on family of USB and Ethernet standard products for regular and automotive applications: USB hubs, Ethernet hubs and switches, USB to Ethernet bridges, display controller with ARM7 core.
Responsible for full chip timing closure (STA) on multiple designs, which included timing constraints (SDC) and various case analysis specifications, supported clock tree synthesis in layout and timing ECOs. Developed PT TCL scripts set, including PT DMSA, which were reused on multiple designs.
Drove chip level DFT insertion, DRC debugging, faults analysis and patterns generation using Synopsys TMAX tool, run patterns verification using DPV methodology. Developed the simulations scripts to automate the patterns verification process - used on multiple designs.
AGERE SYSTEMS (Formerly Lucent Technologies), Allentown, PA
2000-2005
IC Design Engineer/Member of the Technical Staff Enterprise & Networking Div.
2004-2005
Lead IC designer on the USB2.0 Modem Device Controller, which included ARM7 core, DMA controller, USB2.0 device controller, on-chip USB PHY and Codec Digital Link Logic - first silicon was 100% functional.
Completed package and buffers selection, floor planning, pinout, IO ring design and verification, chip size and power estimate to meet USB2 spec tight power requirements.
Supervised custom cells development by specifying requirements, reviewing designs of custom blocks for internal voltage regulators, digital PLL (DPLL) etc.
Supported of USB2 PHY and DPLL integration for offshore RTL design team.
Consulted for offshore verification team to resolve USB2 PHY simulation issues.
Drove the Design for Testing (DFT) methodology by defining test modes, scan test development and integration at the full chip level, developing and debugging all ATE test vectors, to secure optimal ATE testing and maximum test coverage (> 97% for scan).
Performed netlist audits and formal verification with Formality to ensure design integrity.
Developed design constraints for ASTRO Timing Driven Layout (TDL), clock tree synthesis (CTS) to satisfy chip timing requirements
Completed full chip timing closure with Synopsys Primetime to make sure chip is clean from timing violations.
Performed clock jitter SPICE simulations to help identify the source of clock jitter.
RTL and IC Design Engineer, Computer Connectivity Division
2000-2004
Functioned as both RTL designer and IC designer on Modem Codec project for the digital block of the chip, RTL designer for bilingual 1394a/1394b Host/Link design and PHY development, IC designer for USB2.0 discrete PHY for two different technologies.
Performed RTL development/verification and IC design of entire SIO interface and trim control block. RTL designed in Verilog and audited with Verilint.
Designed innovative trimming scheme to aid calibration of critical analog parameters at package parts testing, which significantly reduced production testing time.
Worked closely with analog designers to assure that all design requirements are met.
Built Specman/ncsim/Verdi verification environment, Verilog behavioral model for the fuse block and developed exhaustive verification test suite using Specman e language to create test cases, to ensure design full verification.
Performed design synthesis, netlist audit (Spyglass), clock spine design, timing closure (also used Clockworks) and post layout netlist simulations. Final result - first silicon released to production with no respins.
Acquired knowledge of the 1394a/1394b Fire Wire Standard.
Worked on bilingual 1394a/1394b PHY design partitioning, completed RTL design/verification of 8B10B encoder/scrambler block.
Contributed in RTL design of Fire Wire (bilingual 1394a/1394b) Host/Link design for Apple IP and company standard products responsible for PHY/Link interface design. Contributions included RTL design, netlist audits, and verification. IP used successfully in various products.
Developed design constrains and completed design synthesis for USB2 PHY for two different technologies and performed design formal verification for RTL vs. pre layout and post layout netlist to ensure design integrity.
Utilized knowledge of the USB1.1, USB2.0 serial bus and UTMI I/O protocol specifications to be able to debug ATE testing issues.
Generated and debugged ATE tests for the family of Agere Fire Wire (FW) Standard Products FW80x/FW32x/FW420, including development of tests for speed signaling (common mode signaling tests for differential TPA/TPB for S200 and S400), exploit special 4X ATE test mode for S400 at-speed test to maximize tests coverage and minimize testing costs.
TECHNICAL/PROGRAMMING SKILLS
Verilog and VHDL hardware description languages.
Synopsys PT, PT SI, PT VX, DC, DFTC, TMAX, Formality.
Atrenta SpyGlass for RTL/netlist audit.
Cadence Verilog XL, NC Verilog Simulators
ADVICE (SPICE) circuit simulation tools.
C, Perl, TCL, Pascal, Specman e and assembly languages.
Sprint Verdi debugging tools, waveform viewers: signalscan, MTI, SimVision
Mentor Graphics tessent tool set, testkompress scan compression ATPG tool
EDUCATION AND PROFESSIONAL DEVELOPMENT
Master of Science in Electrical Engineering
City University of New York (CUNY), New York City, NY GPA: 3.7/4.00.
Masters Project: Implementation of the signal processing algorithm - DLX-based image processor system - hardware/software (VHDL/C) co design. Completed graduate level studies of the logic design/analysis, VHDL ALU design, Microprocessors, DSP, Image Processing and Recognition, Cryptology.
Postgraduate Program in Software Engineering
Rzeszow Institute of Technology, Rzeszow, Poland two-semesters program
Master of Science in Electronic Engineering
Academy of Mining and Metallurgy, Krakow, Poland
Company sponsored courses:
Verisity: Specman Basic Training, Advanced Specman Training
Synopsys: Chip Synthesis, Advanced Chip Synthesis, Design For Test (DFT), Basic Verilog with VCS, Advanced Verilog, Verilog Coding Styles for RTL, Chip-level Static Timing Analysis
Novas Debussy Debugging, Sprint Verdi latest features
Mentor Graphics Design for Testing, Silicon Test System
UNIX System Fundamentals
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