Excellent Curriculum Vitae / Resume / Format with Career Objective for B.Tech in( Electronics & Communication Engineering )with 4Months Work Experience in Word / Doc / Pdf Free Download
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CURRICULUM VITAE
SANJIV. R
Ambika Nagar,
Raghunathpur,
Shanti Marg, Email
id : sanjiv@yahoo.co.in
Chittoor(dist), Pin:517151, sanjiv@yahoo.co.in
Andhra Pradesh. Mobile : 9440542091
Objective
|
To pursue a
career in a firm which progresses dynamically and gives me exposure to latest
technologies
and challenging tasks and be a part of the team that excels in work towards the
growth of the organization and gives me a
satisfaction thereof.
Academic Recital
|
Class/Course
|
Name of the
Institution
|
Board
|
Percentage
|
Year of passing
|
B.Tech
(Electronics & Communication)
|
Narayana engineering college
Nellore
|
JNT
university
Hyderabad
|
76.31
|
2006
|
Diploma |
Sri
venkateswara Govt polytechnic,
Tirupathi
|
State Board
of Technical Education and training
|
80.00
|
2002
|
SSC
|
Sri viswodaya
School,
Tirupathi.
|
State Board
of secondary school education
|
67.33
|
1996
|
Technical Skills
|
Languages : C
Operating System : MS-DOS, Windows
XP/NT/2000/98/95
Packages : MATLAB , DSP
Domain knowledge :
Digital
design, Basic electronics, Microprocessors and
Communicatios.
Personal Strengths
|
v
Able to work with a team
v
Working for results with dedication and determination
v
Ability to update knowledge
ACADEMIC
PROJECT
|
Project:
Title : A Parallel Adder Based Realization Of DFT
Using VHDL
Tools
|
:
|
VHDL-simulation
|
Role
|
:
|
Batch
leader & Analysis, design, Testing
|
Team
Size
|
:
|
4
|
Client
|
:
|
Narayana Engineering
College, Nellore
|
Duration
|
:
|
4
months
|
The discrete Fourier transform (DFT) is a key function
widely used in many significant image and signal processing applications.
Because of the high computation complexity, the derivations of efficient
algorithms suitable for very large scale integration (VLSI) are necessary in
many real time applications. A Parallel adder (PA) based design for the
one-dimensional any length DFT is presented.
Using the z transform, an algorithm which can formulate the 1-D any
length DFT as cyclic convolutions is developed.
This algorithm
exhibits higher flexibility in the transform length as compared with the
existing approaches to prime length DFT or power of two DFT designs. The
proposed design uses parallel adders instead of multipliers as well as booth
encoding scheme in the hardware realization for the sake of reducing the
hardware cost, low input-output cost, high computing speed and flexibility in
the transform length.
Personal Profile
|
Name
: RACHAPALLI SANJIV
Father’s name : R . PRAKESH
Date of Birth : 10-07-1981
Gender : male
Languages Known :
English and Telugu
Permanent Address : R. Sanjiv, S/o. R. Prakesh,
Ambika Nagar,
Raghunathpur,
Shanti Marg,
. Chittoor(dist) ,
Andhra pradesh. Pin: 517151
Ph. No : 9440542091
E-mail : sanjiv@yahoo.co.in & sanjiv@yahoo.co.in
Qualities : Ambitious, Optimistic, Wish to handle
tough Challenges
Personal Interests
: Reading Books, watching T.V.
Declaration
|
I here by declare that all the above
details are true to the best of my knowledge
Place:
Date: (R. Sanjiv)
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