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Pranab Yadav

59 Cypress Point Drive, Tulsa FA 22510 +pranab.yadav61@yahoo.com ( (612) 420-3520

Summary

 

·      Research on multi-dimensional digital filter circuits and hardware for wireless digital beamforming applications

·      Experienced in FPGA based digital logic design using VHDL, Xilinx ISE, and Xilinx System Generator

·      Proficient in MATLAB/Simulink, Altera Quartus II, C/C++, and Cadence Virtuoso

·      Experienced in digital circuit analysis using digital signal processing techniques

·      Familiar with mobile communication architecture, CDR generation and server uploads, call and IVR flows

 

Education

 

	Master of Science in Electrical Engineering The University of Akron, Akron, OH Thesis: “Analog and Digital Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications” Advisor: Dr. Arjuna Madanayake	Aug. 09-Feb. 12  GPA: 3.87/4.0
	Bachelors in Electronics and Communication Engineering Tribhuvan University, Kathmandu, Nepal Senior Design Project: “CDMA Network Analysis, Design and Simulation” Advisor: Er. Binit Sharma	Aug. 03-Feb. 08    GPA: 3.98/4.0

Professional Experience

 

Graduate Teaching and Research Assistant Dept. of Electrical and Computer Engineering, The University of Akron, Akron, OH	Aug. 09-Dec. 11
·      Designed a multi-dimensional digital filter capable of filtering carrier-modulated broadband wireless signals depending on their direction of arrivals using Xilinx and Achronix FPGAs ·      Accomplished hardware design of multi-dimensional filter using VHDL, Xilinx System Generator, and Xilinx ISE and synthesized the design for ASIC flow using Cadence Encounter ·      Designed and simulated an analog VLSI circuit for a 2D IIR beam filter using Cadence OrCAD, Cadence Virtuoso, and Spectre ·      Conducted Monte Carlo simulations in MATLAB for measuring bit error rate vs. signal-to-interference ratio of multi-dimensional filters for finite length fixed-point quantizer precisions ·      Administered Circuits I laboratory and assisted students with PSPICE, MATLAB, and AC/DC electrical circuit ·      Conducted lectures and problem sessions on combinational and sequential logic circuits design along with laboratories and design projects assisting students with logic circuits design using VHDL and Altera Quartus II
Application and Software Engineer Huawei Technologies Co., Ltd. Nepal	Aug. 08-July 09
·      Supervised planning, installation, and configuration of Kathmandu Node Customized Ring Back Tone system as a technical implementation manager for Spice Nepal Pvt. Ltd CRBT Project, and United Telecom Limited Nepal ·      Performed site surveys, and designed layout for telecom equipment, and power supply installation ·      Accomplished network planning and IP layout of servers and switches ·      Configured Huawei Media Gateway and Media Gateway Controller for signaling and voice communication ·      Installed and configured Oracle database server, and VERITAS Cluster Server for load sharing ·      Successfully completed CRBT system integration with MSC, HLR, IN, and billing systems ·      Performed regular on-site maintenance of the installed CRBT system and trained customers on the system ·      Prepared method of procedure documents for system upgrades, and regular weekly and monthly update reports

Engineer Intern Nepal Telecom	Sept. 07-Feb. 08
·      Coordinated a 5-member team on a CDMA Network Analysis, Design and Simulation project which involved field visits and surveys, and design of a simulation model in MATLAB for radio frequency signal prediction ·      Attended training on Switching and Gateway System, and CDMA BSS, MSS System at Nepal Telecom

Technical Skills

 

·      VLSI Design Tools: Altera Quartus II, Xilinx ISE, Xilinx System Generator, Mentor Graphics Precision, ModelSim, Achronix CAD Environment, Cadence OrCAD Capture, PSPICE, Cadence IC design environment (Virtuoso Schematic/Layout Editor, Spectre Circuit Simulator) ·      Software Packages & Programming Languages: MATLAB/Simulink, Mathcad, Cisco Packet Tracer, Wireshark, Microsoft Office Package, LaTex, VHDL, Verilog, C/C++, Python, PHP, Assembly language ·      Database: MySQL, Oracle ·      Operating Systems: Microsoft Windows, Linux, Mac OS X

Selected Projects

 

·      Design of a hybrid CPLD-TTL based serial bit-sequence detector using VHDL and Altera Quartus II tool

·      VHDL design of a traffic light controller in Altera Quartus II

·      Developed a MATLAB program to solve the Pocklington integral equation and Hallen equation for the unknown current distribution in an antenna having a finite gap and a finite radius using the method of moments

·      Design of a vocoder using Linear Predictive Coding in MATLAB

·      Developed MATLAB programs for fast and efficient computation of matrix problems and solving systems of linear equations using Advanced Numerical Analysis techniques

·      Design of FIR and IIR filters based on different specifications using windowing techniques in MATLAB

·      Created a client-server based network application using GNU C Compiler capable of handling multiple requests from clients such as document uploads and downloads

Publications   Journals 1.     R. M. Joshi, A. Madanayake, J. Adikari, and L. T. Bruton, “Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications”, IEEE Trans. on VLSI Systems, Jan. 2012. Conferences 1.     A. Madanayake, C. Wijenayake, R. M. Joshi, J. Grover, J. Carletta, J. Adams, T. Hartley, and T. Ogunfunmi, “Teaching Freshmen VHDL-Based Digital Design”, accepted for publication in IEEE International Symposium on Circuits and Systems, ISCAS’12, Seoul, Korea, May 2012. 2.     R. M. Joshi, A. Madanayake, L. T. Bruton, and M. Maini, “Discrete-Space Continuous-Time Analog Circuits for Spatially-Bandpass 2D IIR Beam Filters”, 7th International Workshop on Multidimensional Systems, nDS’11, Poitiers, France, Sept. 2011. 3.     R. M. Joshi, A. Madanayake, and L. T. Bruton, “A 2D IIR Spatially-Bandpass Antenna Beamformer on a 65 nm Achronix SPD60 Asynchronous FPGA”, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS’11, Seoul, Korea, Aug. 2011.

Oral Presentations

 

·      A 2D IIR Spatially-Bandpass Antenna Beamformer on a 65 nm Achronix SPD60 Asynchronous FPGA, 54^th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS’11, Seoul, Korea, Aug. 2011.

·      An Architecture for a 7x7-bit Multiple-Radix Multiplier Block, 54^th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS’11, Seoul, Korea, Aug. 2011.

·      Asynchronous Array Architecture for 16x1 DCT-4/DST-4 on a 65 nm Achronix FPGA, 54^th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS’11, Seoul, Korea, Aug. 2011.

·      Design and FPGA-Implementation of 1st-Order 4D IIR Frequency-Hyperplanar Digital Filters, 54^th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS’11, Seoul, Korea, Aug. 2011.

Honors and Awards

 

·      Outstanding Graduate Teaching Assistant, Dept. of Electrical and Computer Engineering, The University of Akron, Akron, OH, 2011

·      The University of Akron Award of Graduate Scholarship/Fellowship, 2009-2011

·      The College Fellowship, Scholarship and Free Ship, Tribhuvan University, Nepal, 2004-2007

·      Student Scholarship Award for Overall Academic Performance, United Academy, Nepal, 2002-2003

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