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Email: Maya@mac.com   cell phone: 408-307-9876   San Jose, CA

Maya Harrison
Objective: Principal Test Engineer

07Jul2008-25May2011 (3 years) Broadcom Corporation  Santa Clara, CA
Principal Test Engineer, Broadcom Operations
§     Using Verigy 93k ATE platform with Linux/C++ coding, developed production multisite test programs and hardware for Broadcom’s centralized Operations group in a high performance work environment with accelerated time-to-market cycles.  Successfully took products from presilicon dft specification through full characterization and to multisite high volume production release in Asia.  Products included RF devices, and security processors with networking and peripheral interfaces such as sdio, gigabit Ethernet and ddr, as well as gps rf devices which were tested using Verigy RF Portscale.  
§     Platforms included Verigy 93k pinscale test head populated with MCB231’s and MCC226’s; as well as Verigy RF Portscale; large and compact test heads.
§     Analog tests implemented at Broadcom have included M/N coherent ADC/DAC/PGA/filter/gigabit Ethernet phy TX/RX tests and multiple interfaces such as ddr and sdio, as well as standard RF receiver tests such as IP3, imd, and phase noise.  
§     Digital tests implemented at Broadcom have included extensive functional block patterns as well as scan/bist/tapbist/iddq/membist and highspeed interfaces such as ddr/sdio.
§     Designed all supporting boards and hardware for above production testing
§     All of the above development included test list specification, DFT specification, documentation, fixturing and loadboard development, responsibility for proving out repeatability and reproducibility.  Also, datalog-to-database linking, high-volume throughput goals, debug at all phases, and compliance with  time-to-market scheduling needs.
29Sep97–07Jul2008 (10+years)  National Semiconductor  Santa Clara, CA
Principal Test Engineer, Interface/Networking Division
§         Developed digital and mixed signal production test screens on Teradyne Catalyst, Teradyne Tiger, and LTX Fusion HF mixed signal ATE platforms in support of National’s 10/100/1000baseT Ethernet physical layer transceiver  (PHY) product family and RF WLAN devices.  Digital test development experience includes test vector development of standard functional patterns as well as SCAN, BIST, AC (setup/hold), DC (levels, IDD, leakage, continuity), etc..  Mixed signal test development involved both time-domain and frequency-domain postprocessing and employed a variety of standard DSP-based analog and mixed signal test methodologies including undersampling for bandwidth extension, coherent and non-coherent capture schemes, multitone, and waveform time domain analysis such as template testing, risetime/falltime, and overshoot.
§         Interface Timing Products at 3GBPS signal bandwidths: Developed production test and characterization screens for National’s HD/SD SDI Reclocker family, which operate at data rates up to 2.97Gbps. Tests implemented include: 3Gbps at-speed functional and jitter tests, BER tests, eye mask testing, and input jitter tolerance/output jitter tests for both production screening and characterization.
§         Dataconverters: DAC’s/ADC’s  Developed analog and mixed signal production and characterization test programs and supporting ATE hardware for high speed data converters.  Development included specification of Design-For-Test (DFT) features on-chip early in the design phase,  and ATE hardware design and specification of components. Implemented extensive DSP-based test methods across varied product lines, including prime-ratio locked coherent tests in the frequency domain as well as noncoherent testing in the time domain.  ADC tests implemented include sinewave-histogram methods and linear ramp methods:  ENOB, INL, DNL, gain, offset, monotonicity, sparklecode, code density, missing codes.    DAC tests implemented include: SFDR, SNR, SINAD, THD.
§         further block experience:  developed mixed signal test screens for block level analog stages including:  EQ,AGC, DC offset control, amplifiers, echo cancel blocks, and more, including design support on ATE for debug of design issues. Have supporting debug skills working with spectrum analyzers, network analyzers, scopes, bit error rate testers (BERTScope), and automated benchtop software.

15Nov93–22Sep97      International Microelectronics Products                San Jose, CA
Senior Mixed Signal Test Engineer             
§         Design and implementation of production and characterization test programs for mixed signal products including mass storage read channels, programmable filters, and EPAC, a proprietary electronically programmable analog chip family (these chips are analog ASIC’s and FPGA’s with selectable DAC’s/ADC’s/opamps/comparators/attenuators, etc. all on a single chip).
§         DSP-based test development methods were employed throughout the product line, including multitone filter 3dB determination, coherent frequency-domain tests, i.e. THD, SNR, IMD, SFDR, etc., undersampling for system bandwidth extension.
01Jun91–15Nov93              Synergy Semiconductor              Santa Clara, CA
Analog/digital test engineer             
§         Design and implementation of production and characterization test programs for analog ASICS and ultra-fast RAM/LOGIC devices using HP82000, HP83000, Credence LT1201 and Advantest T3331b ATE platforms.
§         Bench and ATE characterization of devices and hardware development
§         interacted with design, process, and marketing groups to work out customer specification issues and various yield issues.

Education:  Class of 1990    San Francisco State University          San Francisco, CA
§         Bachelor of Science in Electrical Engineering.
Concentration: Analog and Digital IC Design (Grey and Meyers, Hodges and Jackson, Sedra and Smith)


ATE Summary:
§         Verigy 93k pinscale/RF portscale, Teradyne Catalyst, Teradyne Tiger, LTX Fusion HF, LTX-AC Synchromaster, LTX-77/DX90, HP83000, HP82000, Tektronix LT1201, Sentry 21, Advantest T3331b
Bench skills: MATLAB, spectrum and network analyzers, BERTscope, scopes, automated bench top software



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