Infineon Technology Sample Resume Format in Word Free Download -->

Infineon Technology Sample Resume Format in Word Free Download

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Sample Template Example of Beautiful Excellent Professional Curriculum Vitae / Resume / CV Format with Career Objective, Job Description, Skills & Work Experience for Freshers & Experienced in Word / Doc / Pdf Free Download
Hannah Dhaliwal

309 Forest Run Road                                                         Telephone: 802-879-9876
Williston, VT 05001                                                          Email: hannah@msn.com

OBJECTIVE:   To be part of a distinguished organization where I can utilize my skills and
    experience in the best possible manner, which can provide ample of
        opportunity for both teamwork and individual contribution.

           
PROFESSIONAL EXPERIENCE
04/2008 - Present    I.B.M Technology, Excess Jct, VT 05452
           
-          Work as an Test & Characterization Engineer on 32 and 28 nm  LP 64M SRAM and 144M SOI edram
-          Write and debug the characterization programs including parametric, functional tests, characterization plans for 32nm,28nm LP SRAM and 22nm edram devices. Evaluate the early hardware and provide feed back to designers in a timely manner.
-          Coordinate new device qualification and support failure analysis of new products. Extensively involved in new product debugging, developing, improve the device yield and validate test instruction using standard characterization techniques as well as providing technical support to manufacturing.
-          Develop complete test programs for validation of memory, Parametric tests, Functional test cases and DFT patterns ( Scan chain, memory BIST, Path delay, memory repair, IDDQ etc) on a chips of different architecture.
-          Perform detail failure analysis on hard and soft fails devices. Recommends solution and improvements for various issue that arise due to process, due to tooling, process and material variables, while minimizing impact through rapid detection time.
-          Perform continuous process improvement for yield improvement and provide engineering support to functional and cross functional teams to meet business objectives and customer requirements.
-          Analyze and profile the effects of manufacturing processes on a product with a main objective of continuously improving quality and increasing product yield.
-          Responsible for preparing engineering spec , test plan, probe card and Module dib  for new product.
                               
11/03 –03/2008    Infineon Technology, Williston, VT 05495
           
-          Worked as a Senior Engineer for a Cellular RAM and MCP memory product. Translate knowledge into solutions, analyze complex situations, apply logic with sound judgment and make decisions on the most effective way to solve the problems, attain goals, and implement solutions.
-          Responsible for tool and flow development and deployment to maximize fault coverage and test quality, facilitate low coverage debug and diagnosis, and minimize test development and application costs.
-          Responsible for test pattern generation and validation and working with the product development team to debug and characterize  product.
-          Determines and develops architecture of new testing methods.
-          Write operating and calibration procedures for new and current equipments.
-          Support, release, and troubleshoot problems, identify underlying issues, and develop solutions to the manufacturing organization.
-          Coordinated new device qualification and support failure analysis of new products, which is extensively involved in new parts debugging, developing test-time reduction strategies, improve the device yield by implementing the shared resources programs.            

01/00 to 07/03     Micron Technology Inc, Boise ID

-          Worked as a Test Engineer for the Flash Memory Product.
-          Implement production test flows for high volume 32 MB, 64MB and 128MB low power Boot Block memory.

-          Develop and implemented parametric, functional and marginal test pattern for high volume wireless flash and Q-series flash products. Some examples of marginal tests include: Low and high voltage stresses that bring out fabrication defects on a silicon, tight timing tests to check the speed of part, tests to characterize reference current and reference voltage related failure on a device, changing trims, different parametric tests to aggravate possible leakage on the parts.

-          Working closely with team of engineers representing design, product engineering, Q/A engineering, probe engineering and backend testing round the clock to achieve device qualification. Work with planning to keep track of the production lots and customer codes.

-          Coordinated new device qualification and support failure analysis of new products. Was extensively involved in new parts debugging, developing test-time reduction strategies, improve the device yield by implementing a 64 site shared resources program.

-          Developed and implemented trending functions and patterns that provide valuable feedback to Design engineer and Product engineer in a timely manner before the parts are subjected to long and expensive backend testing.

-          Performing daily data analysis on high volume production product. Increasing product yield by identifying part problems, identifying and fixing program bugs, develop and running special test flows on Advantest to weed out unusual fails and thus improving the back end yield. 

10/97 to 11/99     Lucent Technologies, Wichita, Kansas( Eng Product)

-          Perform solder ability test on IC leads and In charge of failure Analysis Lab.
-          Participated in building test strategies for embedded Dram:
-          Project included implementation of Cache RAMS and RAs structures              and fuse blown techniques for embedded Dram in accordance with                                   Teradyne J993 testers. Was responsible for first Silicon debugging and   support.
-          Worked on layouts of basic MOSFETs, Inverter and Buffer circuits using 1.5um technology. Layouts of MOSFETs and Buffer were carried out using LASI and the design simulation was carried out using PSPICE.

EDUCATION    Master in Electrical Engineering
                                             Kansas U.S.A.   
                             
SKILLLS   
          
-  Operating Systems:  MS DOS, UNIX, Linux and Windows

-  Language:  C ,C++, Excel, Assembly, HTML, JavaScript, B2 Logic and VHLD

-  Network Technology:  TCP/IP, RIP, IGRP, EIGRP, OSPF, ARP/RARP, Ethernet, Token  
                                           Ring, Frame Relay, FDDI and ATM , Link list.
-  DATA Analysis Skills:   SAS and Excel.
- Tester (ATE) Knowledge:  Teradyne J993, J996 testers, Advantest (5371,5571 &                   5581) and Verigy 93000.

KEY QUALIFICATION
·        Knowledge of Advance Computer Architecture including routers and switches.
·        Excellent communication, interpersonal and organizational skills.
·        Exposure to digital systems testing, and design for test (DFT).
·        Demonstrate strength in technical and analytical problem solving.

TRAINING COURSES
-  GII programming, 5581/5371 programming by Advantest in Boise ID.
-  Special test modes for flash memory devices in Boise ID.
- Experience at Cisco router and switches.
REFERENCES:    Will furnish upon request.

OTHERS:              Willing to relocate and Green Card holder.
                               


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