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Jasica Conklin
152 Wyndridge Lane
Denver, NA. 88499-5370 (720) 324-9085 (m)
Jasica.conklin02@gmail.com

HIGHLIGHTS OF QUALIFICATIONS

  • Expert on Cadence Opus-layout design software, Calibre verification drc/lvs/erc, Simplex emir software
  • Detailed knowledge of verification tools like DRC/LVS as well as CY specific checks like cldrc/soft/stress
  • Top-level chip hook up custom and semi-custom RF Mixes-Signal (Analog/BiPolar/BiCMOS/CMOS).
  • Expert with routing tool: VCR/CCT (Virtuoso Custom Router), Virtuoso VXL and Silicon Ensemble.

PROFESSIONAL EXPERIENCE

Lynmar Design for Cypress Semi, Pocketsonics, and AgigaTech, San Jose, CA.                    4/05/10 – Current
Layout (Consultant)

I worked on a 65nm UMC-only process, creating IO-Ring structures – Pads, IO, & ESD. DRC and LVS done with Calibre.  They were integrated into a test chip.

Worked on an ultrasound mixed-signal front-end chip with dense packing of analog receive channels and memory. The technology was IBM 0.25um CMOS, 2.5V supply. Using VXL I worked on bias generators, preamplifiers, and variable gain amplifiers analog cells.  Layout was highly area constrained and also contained dense custom standard cell digital sections.  DRC and LVS verification were performed using Cadence Assura.

Using VXL, I worked on a 40V opamp and comparator using TSMC18 process.  DRC and LVS used  Calibre.

Agilent Technologies, Santa Clara, CA.                                                                                        9/3/2008-3/05/2010
Layout (Consultant)

I worked on an instrument quality high-resolution multi-GHz ADC.  Its specs for clock jitter, parasitic coupling (crosstalk), and supply noise / supply bypassing far exceeded those for communications chips such as 10Gb/s Ethernet.   Using VXL, I worked on the Analog section that included a Dither Dac and Clock path using BiCmos .13u rules with Cadence and Calibre verification. I laid out the clock input buffer, clock output, transmission lines, level shift, and other related cells.  I have created Bypass cap cells for filling out the power grid.

Micron Semiconductor, San Jose, CA.                                                                                           06/2008 – 08/2008
Layout (Consultant)

Designed Micron full custom layout of a VFERQ_GEN block for the LV_Analog group.  I also did some top level work adding in capacitors etc. using VXL.   Done with Cadence Assura and Hercules, Calibre verification.

Cypress Semiconductor, San Jose, CA.                                                                                          11/2007 – 05/2008
Layout (Consultant)

Designed Cypress full custom layout of I/O power cells using Analog ESD rules.  I laid out the entire gate driver IP, which includes an internal gate driver; an external gate driver and control logic associate to these driver blocks. The external gate driver output goes to a pin, which can driver external component on board level. The internal gate driver is to driver internal power FET.  Used in a power PSoC chip for high brightness LED driver application.
Done in a 350nm 2-layer SONOS process with Cadence Assura and Mentor Calibre verification.

SemiSolutions, Los Gatos, CA.                                                                                                        09/2007 – 10/2007
Layout (Consultant)

SemiSolutions; I modified a test chip using 65nm technology rules adding new structures and correcting the old.
Done with Cadence Assura and Calibre verification.

Crocus –Technology, Sunnyvale, CA.                                                                                            02/2007 - 09/2007
Layout(Consultant)

 Designed Crocus-Technology full custom layout of pitch and Analog related cells using VXL .13um LV-HV for a 1 Meg MRAM.  I did cell and block layout using VXL with some chip planning.  Used Calibre to run LVS DRC.

Qualcomm, San Jose, CA.                                                                                                                04/2006 – 12/2006
Layout (Consultant)

Designed Qualcomm Mems Technologies full custom layout of iMod (interferometric modulation) Panel displays,
based on a MEMS (microelectromechanical systems) structure combined with thin-film optics.  Wire routing, Flex on glass and Process control modules, ran LVS and DRC using ASSURA Cadence software.

Cadence Design Systems, San Jose, CA.                                                                                         10/2005 – 04/2006
Layout (Consultant)

Designed Cadence Design Systems full custom layout of Control blocks used in a Power P.C. (for Xilnix) using 65nm, triple-oxide, 11-layer metal design rules.  Worked from cell to block level , Calibre to run LVS and DRC.

Xilinx, San Jose, CA.                                                                                                                        05/2005 – 10/2006
Layout (Consultant)

Xilnix; Laid out full custom layout of Configuration blocks for the latest generation FPGA, using 65nm, triple-oxide, 11-layer metal design rules. Configuration sub-blocks for the DSP (Digital Signal Processor), MGT (Multi-Giga Bit Transceivers), IOB (I/O Block), and CMT (Clock Management Tile) embedded Blocks of the FPGA.  Worked from Cell to block level and used Calibre Mentor to run LVS and DRC while using Cadence software.

Sun Microsystems, Sunnyvale, CA                                                                                                  03/2003 --07/2004
Mask Designer Specialist 4

Sun; Laid out Tlbmux Block and assisted on the T512 for T.O.1, Completed T16 Block for T.O.2, Panther Ultra Sparc. Laid out Custom cells to fit with Standard cells on a grid, Clock tree and shielding, High Speed 65 nm processes. Mentor Graphics Calibre verification tools (DRC/LVS/Antenna) and Simplex for emir debug.

Cypress/Aspen Semiconductor, San Jose, CA                                                                                06/1988 – 03/2003
Staff Layout Designer

I managed and helped layout, RF Wireless USB (Mixed Signal) 2.4 GHz. Wireless System-on-a-Chip, 2.3 GHz Bluetooth Radio in Bi CMOS, Bluetooth Baseband.   Top level was done with CCAR, VXL, using Cadence with Assura and Calibre verification.
Contributor in the QDR (Quad DATE RATE) bubble logic running at 300mhz.
Key team member on the world class 8Meg MoBL (TAA 70ns) Chip worked the first time:
     - Coordinated the top-level hookup, through final approval.
     - Laid out lower level cells and hooked up the sides of the chip.
Participated in the first Cypress 256k (TAA 6ns) BiCMOS SRAM.  Chip worked on the first revision.
Experienced in laying out chips in several technologies ranging from 2.0um BiCMOS down to 65 nm CMOS.
P&R Semi Custom Layout
Routed timing constrained A/N counters for 2.4GHZ PLL design using Silicon Ensemble.
Performed metal changes on already P&R blocks.
Scheduled and managed layout for the Synchronous NOBL 128KX3:
Routed the middle and bottom with VCR.
Wrote procedure for planning and running VCR.
Supervision/Management
Coordinated layout tasks for 0.25um BiCMOS ISM Band Radio.
Managed the layout and hookup of the Baseband chip in 0.25um CMOS.
Scheduled and Managed Layout tasks for internal and external mask designers.
Responsible for all tapeout paperwork and compliance to Cypress standards.
Training/Methodology
Coauthored and taught a layout class to define latch-up problems and how to correct them.
Cypress tapeout expert with over 100 successful tapeouts.
Converted E-Test modules update processes.
Helped train members of layout group in new skills/procedures.


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