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Sample Template Example of Professional Curriculum Vitae / Resume / CV Format with Career Objective for B.Tech in Electronics & Electrical Engineering with 6+Years Work Experience in Word / Doc / Pdf Free Download
SUNITA  KANDULA.
                                                                        Contact: +91-9876543210.
                                                                        Email: kandula.sunita@gmail.com

OBJECTIVE


            To succeed in an environment of growth and excellence and earn a job indomain of VLSI Design/ Verification which provides me job Satisfaction and self-development and help me achieve personal as well as organization goals.

OVERVIEW

ü  Conceptually strong in Industry Standard EDA Tools for Front-End Design and Verification.
ü  An excellent knowledge of digital design techniques.
ü  Gained professional knowledge and understanding of industrial trends by VLSI Certification Program through Maven Silicon VLSI Design and Training Center.
ü  Experience in writing RTL models in Verilog HDL and Test benches in System Verilog.
ü  Good understanding of the ASIC design flow.
ü  FPGA simulation and verification.
ü  Exposure to a range of FPGA design tools (Xilinx ISE).

TECHNICAL SKILL SET


HDL                                                        :   Verilog.

HVL                                                            :   System Verilog.
EDA TOOLS                                             :Xilinx ISE, Model Sim.
VERIFICATION METHODOLOGIES: Coverage Driven Verification.
DOMAIN                                                  :  ASIC & FPGA Design Flow, Digital Design                                                                                                   methodologies.
FAMILIAR OS                                         :  Windows, UNIX.
KNOWLEDGE                                            :RTL Coding, FSM based design, Simulation, Code                                                                                          Coverage,Functional Coverage, Synthesis.

EDUCATION QUALIFICATION

ü   B.Tech (EEE) in 2010, Secured first class in the college of Dr.PaulRaj Engineering College (Bhadrachalam), JNTU-Hyderabad, Andhra Pradesh, India.
ü    Intermediate in 2006, Secured first class in the College of Raja Junior College, Srikalahasti, Chittoor, Andhra Pradesh, India .
ü  SSC in 2004, Secured first class in the school of Z.P.High School, K.Kandulavari Palli.

VLSI TRAININGPROGRAMME

Certified Advanced VLSI Design and Verification course:from Maven Silicon VLSI Design and Training Center,Bangalore.
Duration                        : Five Months
Expertise                       : ASIC Design – RTL Coding, Verification.

PROJECTS UNDERTAKEN DURING VLSI TRAININ


Project1:

  Title                                     :  Video Graphics Adaptor
  Tools Used                           :  Modelsim, Questa – Verification Platform and ISE
  Language Used                     :  Verilog HDL
  Overview          :  Design a VGA controller to drive VGA display with 640x480 resolution and implement it .CRT based VGA displays use a amplitude modulated moving electron beams to display information on a phosphor- coated screen. This signal based on the horizontal and vertical synchronous based. Display the moving geometric objects.
ü  In this project architected the design.
ü  Implemented the RTL using Verilog HDL.
ü  Verified the RTL using Verilog HDL.
ü  Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board.
ü  Generated Code coverage for the RTL verification sign-off, Synthesized the design.
Project2:
   Title                                     :   Real Time Clock – RTL design and verification.
   Tools Used                          :   Modelsim, Questa – Verification Platform and ISE.
   Language Used                    :   Verilog HDL, System Verilog HVL.
   Synopsis                 :
ü  In this project implemented the Real Time Clock using Verilog HDL independently.
ü  Architected the class based verification environment using System Verilog.
ü  Verified the RTL model using System Verilog.
ü  Generated functional and code coverage for the RTL verification sign-off, Synthesized the design.
Project3:
  Title                                       :  Dual Port RAM – verification
  Tool                           :Modelsim, Questa – Verification Platform
  Language Used                     :  System Verilog HVL
  Synopsis                 :
ü  Architected the class based verification environment using System Verilog.
ü  Verified the RTL model using System Verilog.
ü  Generated functional and code coverage for the RTL verification sign-off, Synthesized the design.

Achievements

ü  Consistent Academic Record.
ü  Participated as a student co-ordination at Techfest-2009 in Dr.PaulRaj Engineering College.
ü  Participated Paper Presentation at SUNFEST-2010 in Sun Flower College of Engineering & technology.

Internal Personal Skills

ü  I would like interest learn new technologies and hardworking nature.
ü  Good coordination & Communication skills.
ü  Ability to work efficiently in a team.
ü  Positive attitude and have proven ability to learn new concepts and technology as warranted.

Internal Personal Skills

            Father                             :  K. Dinesh.
            Date of Birth                  :  06-04-1991.
Nationality                     :  Indian.
Marital Status                :  Single.
Languages Known        :  Telugu, English and Hindi.
Passport                         : Fvailable.

ontact Address           : H.No:8-3-309/285, Plat No: 103,
                                    L N Nagar, Yousufguda,
                                    Hyderabad -500045.                                     

DECLARATION

I hereby declare that the above furnished information is true to best of my knowledge.


                                                                                                                        (Sunita Kandula)
Date:
Place:
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