Electrical Engineer Resume Samples in Word Format Free Download -->

Electrical Engineer Resume Samples in Word Format Free Download

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Sample Template Example of Beautiful Excellent Professional Curriculum Vitae / Resume / CV Format with Career Objective, Job Profile & Work Experience for Freshers & Experienced in Word / Doc / Pdf Free Download
Danna  David
309 Castleview Lane
Garland, TX  75001
(Office) 972-414-1230                 (Cell)  214-783-9876         (Email)  Danna_David@yahoo.com
Objective
Electrical Engineer experienced in signal integrity, verification, and analysis of transistor-level and custom digital integrated circuits. Seeking contract or full-time position in a R&D,  ASIC,  IT group to apply my vast knowledge in the areas of Circuit Design,  Modeling/Programming,  Characterization.   Very detail-oriented.
TECHNICAL SKILLS AND EXPERTISE
¨       Circuit Analysis/Simulation
¨       Verilog/RTL/SpectreVerilog
¨       MCTS 70-431 SQL Server
¨       HSPICE/TI SPICE/Spectre
¨       Noise Analysis (SSO)
¨       CIW Associate Exam 1D0-510
¨       Cell Characterization
¨       IBIS Modeling
¨       Programming in C#, UNIX,  SQL
Professional Experience
2003-PRESENT:  contract POSITIONS & TraininG   (Dallas, TX & San Diego, CA)
¨    Skill Enhancement / Abfitproducts, LLC,  Dallas, TX                                                       (2009-Present)
Expanded my EE hardware profession with IT Training in the areas of SQL Server and C# programming.   Received certification for Microsoft MCTS 70-431 (SQL Server 2005) and CIW Associate.  Currently working part time as Director of Web Planning & Administration for Abfitproducts,  LLC since July 2010. 
¨    QUALCOMM Inc, Corporate R&D Group, San Diego, CA                                                    (2007-2008)
Design Engineer: Responsible for block & top-level simulations and schematics (using Cadence Analog Design Environment, Spectre, SpectreVerilog, BdaSim) for a low-cost (65-nm) SOC Transceiver for a Personal Area Network.  Also wrote specification for Configuration Bus Registers based on own simulations;   and simulated I/O pad ring for SSO noise evaluation.  This was a 3-month contract extended to 7-months.
¨    Samsung Telecommunications America, Richardson, TX                                                               (2006)
Design Engineer: Headed testing/verification of FPGA using USB interface to PC for an error-correction design using Viterbi and Turbo decoding for a 3G cellular system. Also wrote C/C++ code for a GUI interface (using Visual Studio) allowing automated looping for BER vs. SNR datalogs; and ran System-C and MATLAB Simulations on the FPGA design to check Bit & Frame Error Rate (BER & FER) and plotted the corresponding performance curves.  This was a 9-month contract.
¨    Toshiba America Electronic Components, Richardson, TX                                                   (2004-2005)                                                 
Design Engineer: Ran Cadence tools (Simplex/QX) to extract SPICE netlists from layout for a DLP controller ASIC using 110nm technology. HSPICE & Nanosim simulations were run for clock tree skew analysis and DDR interface clock & data critical path timing.   Devised UNIX scripts for post-processing of SPICE output data. Also developed IBIS models using custom HSPICE testbenches for various I/O buffers such as HSTL, LVDS, and PCI-X interfaces.   This ASIC went into full-production on a Samsung TV.   This was originally a short-term (1-month) contract, and was extended to 12 months due to good work.
¨    Mathstar, Inc., Addison & Plano, TX                                                                                                 (2003)
Design Engineer: Responsible for SPICE simulations on various circuits for a 1-GHz FPOA (Field Programmable Object Array) design.  Circuits simulated include:   16-bit   Adder; Shifter critical path; output muxes; and various Dynamic Logic circuits where speed and charge sharing were checked using SPICE.    Also optimized critical design paths; updated schematics using Cadence Virtuoso; and had custom layout training on basic adder cells.   This was a 4-month contract, for simulation only.
1984-2002:   FULL-TIME POSITIONS (Dallas, TX)
Toshiba America Electronic Components,  Richardson, TX                                             (1997-2002)
Senior Design Engineer
¨    Managed ASIC cell-related design issues including ASIC design sign-off; back annotation; critical path SPICE simulations; netlist design rule checks; and generated final netlist for Place & Route.
¨    Automated Toshiba’s cell characterization program to transfer this foreign task to local management.
¨    Conducted independent research and authored IBIS models for PCI/USB interface circuits (as requested by customer) providing them with the necessary IBIS models.
¨    Migrated Toshiba's Z80 IP Core to current process technology.
¨    Worked with key customers to simulate board interconnects (using customer's loading) for driver selection and to guarantee the spec performance.

Texas Instruments,  Dallas, TX                                                                                                  (1984-1997)
  Design Engineer
¨    Lead responsibility for custom cells (RAMS, ROMS and Megacells) used in a MPEG2 audio/video decoder including cell circuit design; ASIC interface person for the backplane integration of custom cells with core logic;  81 MHz SDRAM interface critical path SPICE simulation; and SPICE analysis of back annotated netlists.
¨    Provided key interface expertise between TI and other vendor (1-year on site in Milpitas, CA) to second-source a MPEG2 video decoder with Verilog simulations; SPICE simulations of custom cells; and netlist remapping resulting in successful design transfer to TI.
¨    Contributed collaborative effort with JPEG design team on image compression/decompression processor design consisting of 128x21 dual-port FIFO; Color space converter; and embedded     SRAMs. 
¨    Designed and simulated 20nS/90mA 64K military CMOS SRAMs using noise reduction techniques     and full-chip SPICE on 16K SRAMs leading to patent and contributing to TI’s first working 16K SRAM family.
  Product Engineer
¨    Lead responsibility for 18 ASIC devices consisting of standard cells and gate arrays for 12 major customers.  Responsibility included customer support; spec evaluation; package assembly flows and test programs.
¨    Lead responsibility for 50 CMOS devices (74HC SSI & MSI) in the areas of customer support;     competitor spec evaluations; package assembly flows;  package and process qualifications including autoclave and bias-humidity.  Additionally generated multi-probe and production AC/DC test programs for 50 CMOS devices which made up 30% of TI’s CMOS sales.

                                                           PUBLICATIONS
(1989) U.S. Patent # 4,862,018 (coauthored), February 1989, “Noise Reduction for Output Drivers”.
Patent resulted from SPICE noise simulations for techniques used on 64K SRAMS to reduce output noise when multiple outputs switch simultaneously.
                                                             Education
(1989)  MS, Electrical Engineering, University of Texas at Dallas, Richardson, TX,                 GPA: 3.75/4.00
   Thesis: “Noise Reduction Techniques for CMOS SRAMs”
(1984)  BS, Electrical Engineering, University of Illinois, Champaign, IL,                                GPA: 4.40/5.00


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