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AVINASH BODDU.

Email: avinash@gmail.com.

Phone: 09880613479.

Experience Summary

• 3+ years of experience
• At STMicroelectronics Sophia Antipolis, France, I Worked on ST100 DMA and ARM’s AMBA-AHB using Esterel.
• At TTM India, Hyderabad, I worked on UTMI and memory controller.
• At Strategic-IT, I worked on VB and SQL.
• In MS I was more involved in FPGA’s, all the projects that I worked during my MS are on FPGA’s.

Career Profile

Date	Organization	Role & Responsibilities
2004 jan – 2004 dec	STMicroelectronics, WID, Sophia-Antipolis, France	Programmer
2001 - 2003	TTM India, Hyderabad	Front end designing
2000 - 2001	Strategic-IT	Software Programmer

 

Skill Set

Languages	HDL –VHDL(RTL Coding, Behavioural Modelling) System C, Esterel
Designing Tools	Matlab 6.5, Pspice,ModelSim, visual Elite3.5.0, Esterel v7
Synthesis tools	Synplify Pro7.1, Xilinx ISE
Software Languages	C, C++
Platform & processors	Xilinx Virtex-II pro FPGA, TI C6000 DSP
Operating Systems	Windows 2000/XP, Unix

 

Qualifications

DEGREE	BRANCH	PASSING YEAR	INSTITUTION	UNIVERSITY
Master of Science	System on chip Design	2003-2005	ESIEE-Sophia, France	ESIEE
Bachelor of Engineering	Electronics & Communication	1996-2000	Priyadharshini Engg, vaniyambadi	University of madras
PUC	Mathematics	1994-1996	Vignana Bharathi Tirupati	State Board
SSLC		1994	Jeevashram	CBSE

PROJECTS:

DMA Verification Using Esterel                              

The main objective of the project is to model ST100 DMA and verifying using Esterel Technologies Description: ST100 DMA has 64 channels; channels are divided into two types small channel and full channel. Small channels (160 bits) are used for simple (1D) peripheral/peripheral or peripheral/memory transfers and Full channels (640 bits) for complex (2D) memory /memory transfers. ST100DMA uses 2 priority levels to run channels, fixed priority protocol for high priority channels and Round Robin for Low priority channels. Little and Big data format support. Protections against CPU destructive write access on a running channel and also Half-channels suspend mechanism, Internal and external channel parameters auto-reload mechanism The AMBA AHB bus protocol is designed to use with a central multiplex or interconnection scheme. Using this scheme all bus masters drive out the address and control signals indicating the transfer they wish to perform and the arbiter determines which master has its address and control signals routed to all of the slaves. A central decoder is also required to control the read data and response signal multiplexor, which selects the appropriate signals from the slave that is involved in the transfer.

Responsibilities: Ø  Solely responsible for the Programming the ST100 DMA in Esterel Technologies.

Languages/Tools Used: Esterel Technologies

Company: STMicroelectronics

Genetic Algorithm

The main goal of the Genetic Algorithm is to perform a co-design process, implement on FPGA board (Xilinx 2V pro). The partition between software and hardware is an important goal of this project. Description: In order to save time in microwave simulation algorithms, matrix systems solving has to be fast and accurate. Usually, linear operations are performed over the different rows of a matrix. Random vectors are defined and confronted to the matrix. These vectors are supposed to solve the system, i.e. [M][X]+ [B] = [0], where [B] and [M] are the known matrixes, [X] is the ith vector in a random population, and [0] the null-vector. Each of the random vectors is tested and receives an error-value that is calculated over the components of [Y] = [M] [X] + [B]. The goal is to find the vector [X] such that |[Y]| (we consider it as error) is closer to zero. The best candidates are sorted apart and undergo a crossover operation. New vectors are defined with parents taken from the best-ranked vectors in the previous generation and thus the algorithm goes towards the solution. We used MAT LAB to compare several algorithms of GA that we have proposed.

Responsibilities: Ø  Synthesised the RTL design (VHDL) using Xilinx ISE, targeting Xilinx Virtex2Vpro, for 100 MHz. Ø  The design is simulated using ModelSim. Ø  Team member for Developed the document.

Languages/Tools Used:: VHDL, Virtex 2 VPro, Xilinx ISE, Matlab 6.0,C.

JPEG Compression

This project aims at design a DCT filter for JPEG image. The HW part comprises these items. Filtering and quantization and the rest in SW part. We used Visual Elite to implement it both in system level and transaction level. Description These are the blocks and steps involved in JPEG Compression The formatting of an image into 8x8 blocks of pixels. The filtering of these pixels using the DCT algorithm. The quantization of these filtered data. The compression of these data using the zigzag and the RLE coding. Quantization: The root block is divided into 2 processes, each process manages one 8x8 RAM. The first works with DCT1 then with DCT2 and with the SW module for the acquisition of the block 8x8. The algorithm is as in the following From a given image we read the pixels values. For every pixel, it is a 12-bit signed bits array. In the software part (8*8 block formatting) we extend them to 16-bit signed bits array. Then it sorts those 16-bits signed input pixels as blocks of 8*8 stored in the global RAM. After that the formatting SW signal the IP block that a block is ready. The receiver process in the IP reads a line of 8 pixels and signals the DCT when the data is ready. The DCT filtered the data and signals the quantizer that data is filtered. The second root process work with the quantizer and with the SW module to send back the processed data to the global RAM. The algorithm is as in the following. The quantizer performs the division and signals the transmitter part of the IP interface that data are ready at its output register. The transmitter writes back the data into the 8x8 block matrix in the RAM. The DCT function is separated into 2 HW block named DCT1 and DCT2 to perform the filtering algorithm.

Responsibilities: Ø  I was part of a three member team, I was alone handling the coding of Quantisation at behavioural level. Ø  The design is simulated using ModelSim. Ø  Developed the design document for quantisation.

Languages/Tools Used: VHDL, Synplify Pro7.1

UTMI

The main goal of the project is to program the Transmit and receive protocol Description: This block handles the low level protocol and signalling. This includes features such as data serialization and de-serialization, bit stuffing and clock recovery and synchronization. The primary focus of this block is to shift the clock domain of the data, rate to one that is compatible with the general logic in the ASIC.

Responsibilities: Ø  Transceiver algorithm – Developed RTL model for the Serial Transmission Protocol (STP) and Serial Receiver Protocol (SRP) using VHDL. Ø  Solely responsible for coding

Languages/Tools Used: VHDL

Company: TTMIndia

Memory controller

Description: This block is responsible for the data bus connection between the memory bus and the WISHBONE bus. Data that goes out to the Memory bus is simply latched at appropriate times. Data Read from the memory bus is either passed through a latch to the WISEBONE bus, or goes through a data packet first. The data packet assembles a 32-bit word from 8 or 16 wide device on the memory bus.

Responsibilities: Ø  I was alone handling the coding part of Latch, Packer & parity Programming in VHDL

Languages/Tools Used: VHDL

Company: TTMIndia

 

Training

COURSE DETAILS	DURATION
Clean Room training in ESIEE, PARIS.	2 weeks
Esterel Technologies, Sophia Antipolis, France	1 Month

References : Available on request

 

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