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Vinay Bishnoi                                                                  VEDANT

Phone No. 0172-5080281                           Semi Conductor Complex Ltd. Phase I,

Email:  vinay@yahoo.com                                 Industrial area Mohali Chandigarh.

Mobile No. 09876675101                       

 

CAREER OBJECTIVE:-

                                                To work in a real professional and technical atmosphere that give me an
opportunity to serve the organization with my skills and which helps me in improving and widening the my skills and knowledge.

           

EDUCATION:-

Advanced Post Graduate Diploma in VLSI Design

VEDANT , Semiconductor Complex LTD,Mohali Chandigarh 2006(Currently Pursuing)

Course Structure        :                       Digital Design Technique, Verilog,  VHDL, STA PLD,CMOS                                                  LPD, AMS, DFT,TCL.

Bachelor of Engineering (Electronics & Telecommunication)        (2001-2005)

Rajeev Gandhi Technical  University, Bhopal.                            Percentage 65.44 %.

Higher Secondary School Certificate Examination                          (2000)

M.P. Board Bhopal.                            

High School Certificate Examination.                                                           (1998)

M.P. Board Bhopal                             

SKILL SET:-

HDL Software                        Verilog, VHDL.

EDA Tools                CADENCE Full Flow, Xillinx Web Pack ISE 7.12

Language                    C.

Operating System      LINUX, MS Windows XP/98.

PROJECT DETAILS: -

• Project Undertaken During APGD in VEDANT:-

1.Design of 8-bit RISC processor for FPGA Implementation:-

HDL Used:–                           Verilog

EDA Tools-                            Cadence's NC-Sim (Incisive Simulator)

                                                 Xilinx Synthesis (XST), ISE Web pack 7.1i Implementation Tools

Target Device:-                      Spartan3

Description:-

                        The processor to be designed is a 8-bit RISC processor which is capable of executing 14 instructions including 2 memory access instructions. The design is targeted to run at 200MHz. All the instructions are supported to be executed in single cycle.

2.Design, Simulation and Physical Implementation of 2-bit Full Adder:-

            EDA Tools:                            Virtuso Schematic Composer

                                                            Virtuso Analog Design Environment,

                                                            Spectral simulator,        Virtuso Layout Editor

                                                            Assura physical Verification(DRC , LVS, RCX)

Technology Used:                   GDPK 180nm.

3.Major Project - (Yet to be Finalised)

• Project undertaken during B.E.:-

Signature Verification using Pressure Pattern :-

The project was a part of academic curriculum of the eighth semester of the B.E. course. It is based on concept that every person has his own style of holding the pen, writing angle, and pressure on pen. The overall result of these features causes a different pressure style for each letter or for sign. Therefore by testing both signature pattern and pressure pattern we can identify the person.

INDUSTRIAL TRAINING:-

Communication Department , MPSEB Bhopal, M.P. on power Line Carrier Communication.

Study of Power Line Carrier Communication System.

Examined the Indoor & Outdoor Equipment.

PERSONAL STRENGTH:-

    Positive attitude, Perseverance, Commitment to Task.

PERSONAL DETAILS:-

Hobbies and Interests   :           Playing Computer Games, Cooking.                             Date of Birth                             :           25 April 1983

Reference : 

Vikash Kumar Saha

Software Engineer

vikash_saha@syntelinc.com

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